JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5C DDR5 SDRAM standard. This important update to the JEDEC DDR5 SDRAM standard includes features designed to improve reliability and security and enhance performance in a wide range of applications from high-performance servers to emerging technologies such as AI and machine learning. JESD79-5C is now available for download from the JEDEC website.
JESD79-5C introduces an innovative solution to improve DRAM data integrity called Per-Row Activation Counting (PRAC). PRAC precisely counts DRAM activations on a wordline granularity. When PRAC-enabled DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures. These interrelated actions underpin PRAC's ability to provide a fundamentally accurate and predictable approach for addressing data integrity challenges through close coordination between the DRAM and the system.
Additional features offered in JESD79-5C DDR5 include:
- Expansion of timing parameters definition from 6800 Mbps to 8800 Mbps
- Inclusion of DRAM core timings and Tx/Rx AC timings extended up to 8800 Mbps, compared to the previous version which supported only up to 6400 timing parameters and partial pieces up to 7200 DRAM core timings
- Introduction of Self-Refresh Exit Clock Sync for I/O Training Optimization
- Incorporation of DDP (Dual-Die Package) timings
- Deprecation of PASR (Partial Array Self Refresh) to address security concerns
“I’m delighted to highlight the collaborative efforts of JEDEC’s JC-42 Committee for Solid State Memory to advance the DDR5 standard,” said Mian Quddus, JEDEC Board of Directors Chairman. He added, “Groundbreaking new features in JESD79-5C are intended to support ever-evolving industry demands for security, reliability and performance in a wide range of applications.”
“The JC-42 Committee is pleased to unveil PRAC, a comprehensive solution to help ensure DRAM data integrity, as an integral component of the DDR5 update. Work is underway to incorporate this feature into other DRAM product families within JEDEC,” noted Christopher Cox, JC-42 Committee Chair.
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 350 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit https://www.jedec.org.
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Contacts
Emily Desjardins
emilyd@jedec.org
703-907-7560
